| Eclipse plugins |
|---|
Eclipse Web Update capability allows a vendor to create a custom website specifically for providing updated plug-ins. It is simple for the vendor to track which user uses which version. Eclipse framework provides wizards for creating download site. Eclipse permits providing/preserving vendor specific Perspectives - user specific visual environments.
|
| [Aonix's PERC]: Ultra, Pico, Raven |
|---|
J2EE solution. Support:
- RTS: VxWorks, VxSim, LynxOS, LynxOS-178, Linux, WinNT, WinCE, OSE, OSE Softkernel, QNX, Nucleus, ETS, PikeOS
- Architectures: PowerPC, Intel x86, Xscale, ARM, MIPS, Coldfire
- Hosts: Windows, Linux, Solaris
Performance highlights:
- Compiled - up to 20 time faster than interpreted
- Garbage collection preemption within 100 microseconds
- Direrct Memory API, Scheduled Native Tasks (better performing JNI), Priority Inheritance behaves predictably across targets.
- JNI, RMI, JDBC, Collections, SWT
|
| [OS: Greenhill's INTEGRITY®]: Ultra, Pico, Raven |
|---|
Support:
- C, C++, Ada, FORTRAN
- INTEGRITY 10: Symmetric Multiprocessor, NonUniform Memory Architecture,
- Architectures: ARM/Xscale, Blackfin, 68xx, MIPS, PowerPC, SH, SPARC, StarCore, M32R, V800, x86/Pentium, Coldfire
- Hosts: Windows, Linux, Solaris
Performance highlights:
- The INTEGRITY architectures provides support for multiple Protected Virtual Address Spaces, each of which can contain multiple application tasks. The INTEGRITY kernel is itself protected in its own address space, along with kernel mode tasks.
- Each address space may be assigned fixed budgets of memory and CPU time resources that it is GUARANTEED to have under any circumstances, and beyond which it CANNOT use.
- Hard GUARANTEE that kernel memory will not be exhausted.
- Unique INTEGRITY capability that avoids Priority Inversion and improves RMA ability (RATE MONOTONIC ANALYSIS (RMA)).
|
| [MULTOS - Application Abstract Machine - Smart Cart]
|
|---|
 MULTOS memory layout
 Application data space
|
MULTOS private memory
Static memory is private to the application and cannot be accessed by the terminal or other applications.
MULTOS public memory
The Public memory area is the RAM resident input /output buffer for applications. Incoming APDU (Application DataUnit) are held in Public and any outgoing status word, La and data are placed here. This buffer is also used to pass information from one application to another when delegation is used. As an I/O buffer it is
visible to IFD.
MULTOS guarantees that data in Public remains private to the application until it exits or delegates to another application. So, public may be used as temporary workspace. MULTOS will automatically clean up the public area if the application terminates abnormally, but will not do so otherwise. This means that any data held in Public that an application does not wish to reveal after exiting should be explicitly erased
|
Year 2007 IDEs
- MULTOS Smart Deck Development Kit
- MDS - IDE
Year 2000 IDE for MULTOS:
- GTI has the MULTOS Development Suite available which includes an assembler,
a simulator and a debugger. In addition a very low performance C compiler is
available. Under development are a card loading and application personalisation
module, a terminal simulator,a card probe terminal interface and an improved C
compiler by Q2 2000.
- Hitachi has a MULTOS Application Development Tools which consists of the
MULTOS Assembler and Linker (MALT) and the MULTOS Simulator and Debugger (MSDT). These tools have been announced in September 98, but have not been evaluated thoroughly because of their incompatibility with the others. A C compiler will be launched later this year.
- SwiftCard Technology has developed a toolkit that includes assembler, debugger and optimised C compiler. A beta version of a Java compiler are also available and product is due to be launched in Q2 2000.
|
|
|
|
|
| [MAOSCO]
MAOSCO is a consortium formed in May 1997 to drive the adoption of MULTOS as an open industry-controlled standard. |
|---|
| [Intel ]Hyper-Threading
|
|---|
- Hyper-Threading Technology
Circuitry added to a processor that enables it to appear as two logical processors, resulting in a single physical processor appearing like two logical processors to an operating system and multi-threaded application. Each logical processor can execute a thread of a multi-threaded program. Hyper-threading is Intel's simultaneous multi-threading design. It allows a single processor to manage data as if it were two processors by handling data instructions in parallel rather than one at a time. Hyper-Threading Technology is designed to improve system performance and efficiency.
|
|
|
| [pSOS]
|
|---|
- Merged with VxWorks in 2006. Spin off resulted in RoweBots - Eclipse/C++ IDE.[iZoom]
- DSPnano RTOS for Microchip dsPIC, DSPnano, Unison for Coldfire and for PowerPC
|